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The generally accepted approach to the layout of smart card microcircuit (microcomputer) modules is to place the microprocessor, all types of memory, peripheral modules and the microcomputer I / O unit in a single-chip microcircuit (chip), and not in different chips interconnected by electrical connections.
What is the point of this approach? Firstly, in hiding the connections between the modules of the microcircuit inside one chip and, therefore, in increasing the safety of the operations performed by the microcircuit, as well as the data stored in it. Secondly, in providing a given functionality of a microcomputer in a small-sized microcircuit.
Combining microcircuit modules in one crystal makes it difficult for an outside observer to intercept signals transmitted between individual microcircuit modules, since in this case the physical connections between microcomputer components are laid on the surface of a monolithic silicon structure and have microscopic dimensions.
If a smart card computer consisted of more than one chip, then the connections between the chips would represent obvious attack spots. If the signals transmitted over the connections between the chips are not protected, then they can be intercepted by a third party.
It is safe to say that the need for secure portable media that can store information and provide a secure platform for some computing activity has prompted the development of smart cards. Due to the high security of the hardware and software platform of a smart card, it is often used as a reliable means of identification and authentication of its holder, as well as for performing cryptographic operations in a protected mode (Hardware Security Module, or HSM device mode).
HSM protected mode is understood to mean that the card performs cryptographic calculations physically protected from an external observer and the secure storage of secret keys. In this case, it is a card application called a Security Application Module (SAM). As a security module smart card
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it is used in many systems / devices, for example, in some models of POS terminals.
A well-known example of the use of the IPC for identification / authentication of the cardholder is the SIM card of a cell phone, which performs the function of authenticating the owner of the phone and protecting the information transmitted over the GSM channel.
The small size of the microcircuit allows it to be placed in the body of a plastic card. When using and storing the card (for example, in a wallet), a chip built into a plastic card is subjected to various physical influences: the card bends in different directions, it can be twisted. In conventional electronic equipment, in which components are connected to each other by electrical wiring, and even in the case of the implementation of connecting lines on a printed circuit board, such a physical environment is the cause of many malfunctions.
When the modules of a chip are packed in a single chip, the load is applied to all the elements approximately equally. Thus, if the chip as a whole can survive, then its components are likely to be functional. Empirical observations show that if the chip is reduced to about 25 mm 2 with a nearly square chip shape, it can withstand the daily stresses that are put on it in typical card use.
The size of the chip embedded in a smart card depends on a number of factors:
Today technologies with design standards of 0.22, 0.18, 0.13 microns are considered standard. Using technology with a design standard of 0.13 microns on a chip of less than 25 square millimeters, Infineon managed to accommodate a 32-bit processor, 32 KB RAM, 256 KB ROM, 660 KB EEPROM, cryptographic coprocessors and others in its SLE88CNX6602PM product peripheral microcircuit modules.
A number of companies have announced the launch of the production of chips used in smart cards with a design standard of 0.08 microns. Such microcircuits already contain nano-objects and can significantly expand the capabilities of a smart card. It is expected that by 2015 the technological level of microelectronic products will reach 0.045 microns (45 nanometers).
However, in order to make chips inexpensive and reliable, chip designers often turn to old and proven technologies instead of using the aforementioned expensive methods of manufacturing them. For example, you can optimize the chip size by making the best use of the different types of card memory. As shown in fig. 2.5, the sizes of the chip areas required to create different types of memory differ significantly from each other. Obviously, to optimize the chip size, you need to save on RAM and try, if possible, to place all static program data (operating system, unchanged throughout the life cycle of the application card) in the most economical ROM memory.
FRAM
Rice. 2.5. Comparative sizes of implementation on a chip of various types of 1-bit memory
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There are also special algorithmic methods for saving RAM memory. Obviously, the use of such methods leads to a decrease in the performance of card applications.
The central processor of the microcircuit can work with no more than a certain amount of RAM (address space of the processor). The size of the address space is determined by the width of the address bus of the system bus (the number of lines in the address bus). If the number of lines in the address bus is equal to m, then the volume of the addressed memory is equal to 2 t bits. The minimization of the chip size also results in the selection of a smaller number of addressing lines. Most often, 8-, 16-, and 24-bit address buses are used, which allow the processor to work with machine words of 256, 65536, and 16,777,216 bits, respectively, at any given time.
The microprocessor is the heart of the smart card chip. It is characterized by bit depth, clock frequency and architecture.
The bit width of the processor is the maximum number of bits of information that can be simultaneously processed by the processor. Microprocessor cards use 8-, 16- and 32-bit processors. The speed of operations depends on the bitness of the processor. The higher the bit capacity of the processor, the more information it can process per unit of time, the higher its efficiency. For example, the speed of a multiplication operation in the first approximation is proportional to the square of the processor bit capacity, and the speed of an addition or register shift operation depends on the processor bit capacity according to a linear law.
Today, 8- and 16-bit processors are the most widely used in IPCs. 16-bit RISC processors are widely used in multi-application cards, especially Java cards. There is supply and demand in the market for 32-bit processors, which are likely to become the norm in a few years.
The work of the processor (as well as of other components of the microcircuit) is synchronized by the clock frequency pulses from the master oscillator. The processor clock speed is defined as the maximum time the processor can perform an elementary action. The higher the clock frequency of the processor, the higher its performance. Therefore, clock speed is the most important characteristic of a processor. The clock speed of the processors used in microprocessor cards usually ranges from 1 to 33 MHz. If we talk about record shifts, then they use higher frequency values. For example, Infineon's SLE88CFX series chips use a 32-bit processor clocked at up to 66 MHz.
The use of a clock frequency of 30 MHz makes it possible to increase the speed of execution of machine instructions by 6-10 times in comparison with the first microprocessors operating from a reader signal with a clock frequency of 3-5 MHz.
The clock generator can be external or internal for the microcircuit. In the first case, the microcircuit receives a clock signal from the reader through the CLK contact. In the second case, the microcircuit has its own internal clock (clock generator).
The first microcircuits did not have their own clock. To ensure the operation of the processor and other elements of the microcircuit, as well as the functioning of communication protocols, an external clock signal of the reader was used, fed to the card through the CLK contact. The signal had a frequency in the range from 1 to 5 MHz. In practice, two frequencies are widely used - 3.579545 and 4.9152 MHz. The popularity of these clock frequency values is associated, firstly, with the cheapness of crystals generating such frequencies, and secondly, with the fact that the considered frequency values have integer dividers (372 and 512, respectively), which makes it easy to implement the common in card communications baud rate 9600 bps.
The cheapness of crystals was determined by their widespread use in industry. For example, crystals with a frequency of 3.579545 MHz are used to transmit the color subcarrier in the American television standard NTSC. It is for this reason that most terminals have readers using the mentioned frequencies. Modern readers generate an external clock signal with a frequency of 1 to 10 MHz when establishing a connection with a card.
On the other hand, low external clock rates have become a bottleneck over time for improving performance. Retrofitting a large fleet of terminals to replace higher clock speed readers was difficult and costly. The solution to the problem was the use of the microcircuit's own clock or the use of special hardware and software of the microcircuit to increase the clock frequency of the external generator by an integer number of times. Most often, in modern microcircuits, the processor and other components of the microcircuit operate at the clock frequency of the internal clock of the chip,
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and the input clock signal is used only for communication between the card and the terminal. At the same time, the universal asynchronous transceiver of the microcircuit (UART) supports the frequency multiplication of the external signal in order to ensure the required data transfer rate between the reader and the card.
The architecture of the IPC processor is mainly determined by the system of commands used and addressing methods. Microprocessor cards mainly use RISC processors that support Reduced Instruction Set Computer (RISC). This set usually consists of 20-80 commands, which include arithmetic operations, logical commands, address operations, data transfer commands, I / O commands, control commands, etc. The command system has been simplified and reduced to such an extent that each the command is executed in one clock cycle. This approach improves processor performance.
Today, the Motorola 6805 and Intel 8051 instruction sets are typical of many processors. These instruction sets usually have an addition of memory and register operations, support for addressing and I / O modes, and instructions used exclusively in smart cards.
The largest manufacturers of microprocessors for smart cards are Infineon Technologies AG, Renesas Technology (a joint venture between Hitachi and Mitsubishi), STMicroelectronics, NXP Semiconductors, Motorola, NEC, Atmel, Samsung Electronics.
In microprocessor cards, symmetric and asymmetric cryptographic algorithms are used to ensure the integrity and confidentiality of transmitted data, authenticate the information source, and calculate cryptograms (data signatures consisting of card, terminal and transaction details) (see Appendix B). As a symmetric encryption algorithm, in the overwhelming majority of cases, the block algorithm Triple DES (or 3DES) is used, which has a key length of 112 bits and encrypts blocks of 64 bits. As an asymmetric encryption algorithm, the RSA algorithm is used with a public key modulus ranging from 1024 to 1984 bits.
The symmetric encryption algorithm is based on the use of permutations, substitutions and nonlinear table transformations of individual elements of the encrypted data blocks (see Appendix B). These are simple operations that can be accomplished in a reasonable amount of time using the standard instruction set of the card's CPU. For example, encrypting a 64-bit block with DES (used three times in 3DES) on an 8-bit 3.57 MHz processor takes about 10 ms and requires about 1 KB of ROM to store the DES program and related to it static data (tables of substitutions, permutations and S-transformations). The same encryption operation on a 32-bit 33 MHz processor takes about 100 μs.
To increase the speed of cryptographic computations, microcircuits use special processors called cryptographic coprocessors or cryptoprocessors. Crypto processors are designed to perform a reduced set of special operations used in cryptographic algorithms. In the case of a cryptoprocessor for the implementation of the 3DES algorithm, such operations are the already mentioned permutations, substitutions, and table transformations. Due to the support of a limited set of special operations, the execution time of cryptographic algorithms on a cryptoprocessor is reduced. For example, the implementation of DES on a 33 MHz cryptoprocessor takes 3.5 microseconds, which is about 30 times faster than on a 32-bit CPU with the same clock speed.
Considering that the EMV application during the processing of an online transaction can use the DES algorithm more than 40 times (outputting session keys, ICC Dynamic Number values, calculating ARQC and TC / AAC cryptograms, MAC (Message Authentication Code) verification in Issuer Script Processing commands, encryption of offline counters; for more details, see Chapter 4) even in modern microcircuits using high values of the internal clock frequency, it is customary to use cryptoprocessors - accelerators of the 3DES algorithm. At the same time, it should be recognized that for many applications, including EMV, on modern microcircuits the 3DES algorithm can also be implemented by the microcircuit's central processor.
The situation changes radically in the case of the RSA algorithm. It is known that the implementation of an asymmetric encryption algorithm takes two orders of magnitude (about 100 times) more time than a symmetric one with the same cryptographic strength. The RSA algorithm actively uses block-wise multiplication of two large numbers modulo a large number. This operation requires the presence in the processor instruction system of non-standard instructions for block multiplication and decreasing the obtained
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result by a multiple of some large fixed number. Without support for such special commands, a standard 8-bit processor on the microcircuit will execute the RSA algorithm using a 1024-bit public key module for 10-20 seconds. Taking into account that the total transaction processing time should not exceed 3 s, the option of using the main processor of the microcircuit for RSA implementation immediately disappears.
As a result, a cryptographic coprocessor is used, which allows, when operating at a clock frequency of 33 MHz, to perform encryption on a private (long) key in tens of milliseconds and on an open (short) key in a few milliseconds. Generation of an RSA key pair occurs in less than 10 seconds. The data presented refers to computations with a public key modulus of 1024 bits.
Table 2.1 shows the values of the encryption time on the private and public keys of the RSA algorithm with a public key modulus of 1024 bits for some Infineon microcircuits.
Tab. 2.1. Typical values of the execution times of the RSA algorithm
Table 2.2 shows the execution times of various operations of the RSA algorithm on the Crypto @ 1408Bit crypto processor used in the SLE88CFX1M00P and SLE88CFX8002P microcircuits from Infineon. This crypto processor has its own 880 bytes RAM.
Tab. 2.2. Execution Timing RSA
Note that the speed of RSA operations is linearly dependent on the clock frequency of the crypto processor. The generation time for RSA keys is a random variable (see the description of the algorithm in Appendix B), therefore the table shows the average values of this indicator. Finally, note that the exponent value of the public key F_4 is used = 2 16 + 1 = 65537 (Fermat's number is 2 2 + 1 for n = 4).
Cryptographic coprocessors are designed to perform arithmetic operations on large numbers and have their own RAM for performing such operations. The presence of a cryptographic coprocessor in a chip means an increase in the size of the chip, and hence an increase in the cost of the card. Today, this rise in price is on average 20-30 eurocents per card when purchasing a batch of 10,000 cards (with an increase in the volume of purchases, the difference decreases).
When a smart card implements a number of procedures, random numbers generated by the card are used. An example is the procedures for generating an RSA public / private key pair and encrypting the cardholder PIN. An algorithm or procedure for generating random numbers is usually implemented in a separate module on the chip called a Random Number Generator (RNG). Of course, the concept of an algorithm, each step of which gives a deterministic result, contradicts the concept of randomness. Therefore, RNG software implementations have an inherent flaw and generate only pseudo-random numbers. However, if the range of values of the pseudo-random number generator and the period of their repetition are large, then such an implementation can be considered acceptable.
Along with software implementations of the random number generator, there are hardware implementations that use physical variable parameters of the microcircuit, for example, the characteristics of the thermal noise of the microcircuit. Hardware implementation is preferable to software implementation, since it generates a sequence of numbers that cannot be calculated using any deterministic algorithm. In this sense, the numbers obtained are truly unpredictable, that is, random. Therefore, microcircuit modules that implement random number generators in hardware are called True Random Generator (TRNG). FIPS 140-2 (Federal Information Processing Standards, Publication 140-2) describes randomness tests for a sequence of numbers generated by a random number generator.
To implement a random number generator in a microcircuit, a separate coprocessor is usually used.
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A separate coprocessor is also used to implement the module for calculating the check sequence of a cyclic code described by the ISO / IEC 3309 standard. (For the characteristics of this code and its use in the T = 1 communication protocol, see clause 2.4.2.) This module can also be used for ensuring the integrity of the information stored in the EEPROM memory.
The cheapest type of non-volatile memory is ROM (Read-Only Memory). This memory is also known as ROM (Read Only Memory). In it, an array of cells is a set of conductors organized into a matrix structure (some conductors are rows of such a structure, and some are columns). Some conductors remain intact, and some are destroyed during the "burning" of the ROM mask corresponding to the application that will be stored in the ROM.
The closed state of the conductor can be assigned the value of a logical zero, and the open state - a logical one. If we now measure the voltage between one of the lines of the columns and one of the lines of the rows (i.e., access a specific memory cell), then its high value (open state of the conductor) corresponds to a logical unit, and zero (closed state of the conductor) to logical zero ...
There are other ways to create a ROM mask. The most famous of these is the Implantation ROM method, in which the memory is encoded by irradiating the surface of the crystal occupied by the ROM with a powerful ion beam.
The main disadvantage of ROM is the impossibility of updating the contents of memory cells, i.e., the impossibility of recording / updating information during the operation of the card. Therefore, in smart cards, ROM is loaded with the operating system of the card and static applications (applications that do not require changes during the life cycle of the card). In particular, ROM stores all utility programs, including programs for maintaining the file system of the card and providing communication, performing cryptographic operations. These programs are written ("stitched") into the ROM during the manufacture of the card and cannot be changed later.
General purpose smart cards have ROMs ranging in size from 16 to 196 KB. The ROM size in record-breaking cards exceeds 256 Kb.
RAM (or otherwise operating memory) is the volatile and most expensive memory in a smart card.
It is used by the processor to store fragments of executable code and intermediate data when performing various operations, since it is the fastest form of memory for reading and writing data. The access time (the period of time during which the contents of one memory cell can be read or written) of RAM is several tens of nanoseconds. The speed of processor operations depends on the size of the RAM memory (sometimes, due to the small size of the RAM memory, you have to split one operation into several sequential operations, which increases the execution time).
Hard limits on RAM size are the most sensitive in terms of writing card applications. Even the use of high-level languages makes developing smart card applications an art to be learned. The programmer is constantly forced to economically use temporary variables or even invent special algorithms to implement operations using large variables.
Moreover, RAM is used by both the programmer's applications and all the utilities of the card, and the programmer must know not only how much RAM is used by his applications, but also how much memory is required for the utilities that his applications access during their execution. This is why, despite the emergence of open platforms Java Card and MULTOS, enabling millions of software developers to write smart card applications, this is still the domain of smart card vendors.
As shown in fig. 2.5, the size of the crystal areas occupied by RAM and ROM, necessary to store the same amount of information, are approximately 16: 1. To a first approximation, the cost of a microcircuit component is proportional to the area of the crystal it occupies. Therefore, the increase in the cost of the card with the increase in the size of the RAM memory is the fastest in comparison with other types of memory.
Champion cards (usually Java cards) have a RAM size of 4 to 8 KB, although for many payment applications (supporting only DES and T = 0 protocol) it is sufficient to have a memory size of several hundred bytes. Record-breaking cards (for example, the already mentioned cards of the SLE88 family from Infineon) have 16 KB of RAM, and the SLE88CNFX6602PM card even has 32 KB.
There is another type of non-volatile rewritable memory widely used in smart cards - EEPROM memory. Unit
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this memory is about four times cheaper than a RAM unit and four times more expensive than a ROM unit. The EEPROM can house some of the card applications, as well as store the operating system data of the card and all configuration and variable data of the card applications, regardless of whether these applications are stored in ROM or EEPROM. Obviously, this is due to the fact that EEPROM is the only rewritable and at the same time non-volatile type of memory on a smart card. When the card is powered off, the data written to the EEPROM can be stored for more than ten years.
EEPROM memory has two significant limitations. The first is the limited memory performance. It usually takes 2 to 10 ms to erase and then write data to the EEPROM (programming time).
The second limitation is related to the wear and tear of this type of memory. EEPROM memory becomes unusable after a certain number of data rewriting cycles (about 100-500 thousand cycles).
Recently, card manufacturers have been paying more and more attention to flash memory as an alternative to ROM and EEPROM. This type of memory is about twice as economical as EEPROM memory and twice as expensive as ROM memory. At the same time, flash memory has many important advantages. As compared to EEPROM memory, the advantages of flash memory lie in a significant increase in the speed of memory and in the absence of its wear (you can rewrite data almost an unlimited number of times).
Compared to ROM, the main advantage of flash memory is that it eliminates the need to create a map mask. The operating system of the card and applications can be loaded into flash memory just like normal software. In this case, the area of the flash memory used as a ROM, after downloading the software, for security reasons must be securely closed against changes / modifications.
An important issue for the use of smart cards is the problem of ensuring the integrity of the information stored on the card when the transaction is interrupted. Since the card can be removed from the terminal's reader at any time during the execution of a transaction, this can happen in the middle of the calculations associated with the card's implementation of some function of its application. This card extraction is called a break. If a rupture has occurred, it is important that the information in the microcircuit does not remain in a state of unfinished operation. In particular, if the card supports the functionality of an electronic wallet, then it is important that upon a rupture, the amount of the wallet does not turn out to be higher than at the beginning of the operation. Otherwise, it will become an obvious way of committing fraud.
A number of gap-bridging mechanisms are employed in smart cards. The most general is a mechanism similar to the mechanism adopted in database management systems and consists of the following. At the beginning of the operation, the "transaction flag" is set and the most important application parameters at that moment are stored in the EEPROM. This flag and its associated data are cleared only at the end of the operation. If at the beginning of the next operation a set "transaction flag" is noticed, this will indicate that the previous transaction was aborted and not completed. When this state is recognized, the application settings are "rolled back" to the state at the beginning of the previous transaction, and only then the new operation starts.
The integrity of the most important information stored on the card, such as keys, cardholder personal data, etc., is ensured by the card's hardware and software. Special sensors of the microcircuit prohibit changing the memory of the microcircuit if the processor does not process the data write command. In addition, the operating system of the card uses check sequences to detect the fact that the integrity of the stored information has been violated.
The I / O channel of the smart card chip is a unidirectional serial interface. This means that at a time, only 1 bit of information can be transmitted along it and it can only be transmitted in one direction (half-duplex communication). In accordance with the ISO / IEC 7816-3 standard, data exchange between the smart card and the reader can be carried out at a speed of up to 115,200 bps. Modern contact cards support baud rates of 9600, 19,200, 38,400, 55,800, 76,800 bps and higher. The baud rate supported by the card is determined by the ability of the asynchronous transceiver to multiply the frequency of the external clock signal or internal clock (see section 2.3). Many UARTs support 4x, 8x, 16x clock frequency multiplication.
To organize data transfer between the reader and the card, two lines of the card interface are used. One of the lines, the I / O line (I / O lines), carries the data bits. The second line, the clock line (CLK line), indicates when to sample the I / O line to obtain a data bit.
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The USB interface uses two additional lines to form a second I / O channel. In this way, a duplex connection is created.
A duplex SWP (Single Wire Protocol) connection is established over one line using pin C6. The typical data exchange rate for such a connection is 1.5 Mbit / s.
The communication protocol between the reader and the smart card uses the relationship between the user (reader) and the server (smart card). The reader sends commands to the card and receives responses from it. The smart card never sends data to the reader, except in response to his command.
The standard link layer protocols (T = O, T = 1, T = CL) used between the reader and the card are half duplex. This means that data is either supplied to the I / O line by the reader and read by the card, or supplied by the card and read by the reader. Thus, each participant in the data exchange (reader and terminal) keeps track of whether it is in the transmitting state or in the receiving state.
The communication protocols used are not complex, and therefore complete - taking into account all possible situations. Therefore, a case is possible when, for example, the reception of an erroneous message leads one or both sides of the data exchange to an undefined state. When this happens, it is the responsibility of the reader to restart the card to correct the line failure.
Smart card operating systems support character-by-character and / or block-by-block communication. (For more details, see section 2.4.)
There are smart cards on the market that support work with the terminal via the USB protocol, which provides full-duplex data transfer at speeds up to 12 Mbit / s. It should be noted that the weak communication capabilities of today's microprocessor cards are one of the main limitations for expanding the area of their use. Improving the communication characteristics of a smart card (duplex nature of the exchange, support for a stack of Internet protocols, including TCP / IP, increasing the data transfer rate) will make a smart card an independent device capable of direct dialogue with network computers.
Power is supplied to the card from the reader. All smart cards used today can operate at a supply voltage of 5 volts and 3 volts (more precisely, in accordance with section 5.3.6 of book 1 of the EMV 4.2 standard, the card must support voltages in the range from 4.5 to 5.5 volts and from 2, 7 to 3.3 volts). Some microcircuits are capable of operating at lower supply voltages, namely at 1.8 volts.
In June 2009, the migration of cards supporting only 5 volt supply voltage to cards supporting two voltage values - 5 and 3 volts, and cards supporting three voltage values - 5, 3 and 1.8 volts was completed. Thus, cards supporting a single supply voltage of 5 volts are out of circulation.
As a result, today servicing banks / merchants can install terminals that support only 3 volts or two voltage values - 3 volts and 1.8 volts. However, terminals that only support 5 volts remain functional and there are no plans to retire these terminals. To date, EMVCo, the company that manages EMV specifications, has not developed a plan to start installing terminals whose readers only support 1.8 volts.
The choice of the operating voltage value supplied to the card is determined as follows. If the terminal supports multiple supply voltages, the smallest value (1.8 or 3 volts) is applied to the VCC pin of the microprocessor card. If a voltage of 1.8 volts was applied and within a certain time interval the terminal does not receive an ATR sequence from the card (see p. 2.3), it supplies the card with a supply voltage of 3 volts.
What is the point of this approach? Firstly, in hiding the connections between the modules of the microcircuit inside one chip and, therefore, in increasing the safety of the operations performed by the microcircuit, as well as the data stored in it. Secondly, in providing a given functionality of a microcomputer in a small-sized microcircuit.
Combining microcircuit modules in one crystal makes it difficult for an outside observer to intercept signals transmitted between individual microcircuit modules, since in this case the physical connections between microcomputer components are laid on the surface of a monolithic silicon structure and have microscopic dimensions.
If a smart card computer consisted of more than one chip, then the connections between the chips would represent obvious attack spots. If the signals transmitted over the connections between the chips are not protected, then they can be intercepted by a third party.
It is safe to say that the need for secure portable media that can store information and provide a secure platform for some computing activity has prompted the development of smart cards. Due to the high security of the hardware and software platform of a smart card, it is often used as a reliable means of identification and authentication of its holder, as well as for performing cryptographic operations in a protected mode (Hardware Security Module, or HSM device mode).
HSM protected mode is understood to mean that the card performs cryptographic calculations physically protected from an external observer and the secure storage of secret keys. In this case, it is a card application called a Security Application Module (SAM). As a security module smart card
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it is used in many systems / devices, for example, in some models of POS terminals.
A well-known example of the use of the IPC for identification / authentication of the cardholder is the SIM card of a cell phone, which performs the function of authenticating the owner of the phone and protecting the information transmitted over the GSM channel.
The small size of the microcircuit allows it to be placed in the body of a plastic card. When using and storing the card (for example, in a wallet), a chip built into a plastic card is subjected to various physical influences: the card bends in different directions, it can be twisted. In conventional electronic equipment, in which components are connected to each other by electrical wiring, and even in the case of the implementation of connecting lines on a printed circuit board, such a physical environment is the cause of many malfunctions.
When the modules of a chip are packed in a single chip, the load is applied to all the elements approximately equally. Thus, if the chip as a whole can survive, then its components are likely to be functional. Empirical observations show that if the chip is reduced to about 25 mm 2 with a nearly square chip shape, it can withstand the daily stresses that are put on it in typical card use.
The size of the chip embedded in a smart card depends on a number of factors:
- the technology used to create a chip, which is characterized by the "element size" (for example, the size of one transistor element) in the chip;
- types and sizes of memory used in the microcircuit;
- the width of the main bus of the microcircuit (8-, 16-, 32- and 64-bit buses are used);
- the presence of additional elements (coprocessors, random number generators, voltage filters, temperature sensors, memory management module, etc.) included in the chip to fulfill the functional and operational requirements imposed on it, as well as to ensure the security of the microcircuit and card transactions.
Today technologies with design standards of 0.22, 0.18, 0.13 microns are considered standard. Using technology with a design standard of 0.13 microns on a chip of less than 25 square millimeters, Infineon managed to accommodate a 32-bit processor, 32 KB RAM, 256 KB ROM, 660 KB EEPROM, cryptographic coprocessors and others in its SLE88CNX6602PM product peripheral microcircuit modules.
A number of companies have announced the launch of the production of chips used in smart cards with a design standard of 0.08 microns. Such microcircuits already contain nano-objects and can significantly expand the capabilities of a smart card. It is expected that by 2015 the technological level of microelectronic products will reach 0.045 microns (45 nanometers).
However, in order to make chips inexpensive and reliable, chip designers often turn to old and proven technologies instead of using the aforementioned expensive methods of manufacturing them. For example, you can optimize the chip size by making the best use of the different types of card memory. As shown in fig. 2.5, the sizes of the chip areas required to create different types of memory differ significantly from each other. Obviously, to optimize the chip size, you need to save on RAM and try, if possible, to place all static program data (operating system, unchanged throughout the life cycle of the application card) in the most economical ROM memory.
FRAM
Rice. 2.5. Comparative sizes of implementation on a chip of various types of 1-bit memory
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There are also special algorithmic methods for saving RAM memory. Obviously, the use of such methods leads to a decrease in the performance of card applications.
The central processor of the microcircuit can work with no more than a certain amount of RAM (address space of the processor). The size of the address space is determined by the width of the address bus of the system bus (the number of lines in the address bus). If the number of lines in the address bus is equal to m, then the volume of the addressed memory is equal to 2 t bits. The minimization of the chip size also results in the selection of a smaller number of addressing lines. Most often, 8-, 16-, and 24-bit address buses are used, which allow the processor to work with machine words of 256, 65536, and 16,777,216 bits, respectively, at any given time.
The microprocessor is the heart of the smart card chip. It is characterized by bit depth, clock frequency and architecture.
The bit width of the processor is the maximum number of bits of information that can be simultaneously processed by the processor. Microprocessor cards use 8-, 16- and 32-bit processors. The speed of operations depends on the bitness of the processor. The higher the bit capacity of the processor, the more information it can process per unit of time, the higher its efficiency. For example, the speed of a multiplication operation in the first approximation is proportional to the square of the processor bit capacity, and the speed of an addition or register shift operation depends on the processor bit capacity according to a linear law.
Today, 8- and 16-bit processors are the most widely used in IPCs. 16-bit RISC processors are widely used in multi-application cards, especially Java cards. There is supply and demand in the market for 32-bit processors, which are likely to become the norm in a few years.
The work of the processor (as well as of other components of the microcircuit) is synchronized by the clock frequency pulses from the master oscillator. The processor clock speed is defined as the maximum time the processor can perform an elementary action. The higher the clock frequency of the processor, the higher its performance. Therefore, clock speed is the most important characteristic of a processor. The clock speed of the processors used in microprocessor cards usually ranges from 1 to 33 MHz. If we talk about record shifts, then they use higher frequency values. For example, Infineon's SLE88CFX series chips use a 32-bit processor clocked at up to 66 MHz.
The use of a clock frequency of 30 MHz makes it possible to increase the speed of execution of machine instructions by 6-10 times in comparison with the first microprocessors operating from a reader signal with a clock frequency of 3-5 MHz.
The clock generator can be external or internal for the microcircuit. In the first case, the microcircuit receives a clock signal from the reader through the CLK contact. In the second case, the microcircuit has its own internal clock (clock generator).
The first microcircuits did not have their own clock. To ensure the operation of the processor and other elements of the microcircuit, as well as the functioning of communication protocols, an external clock signal of the reader was used, fed to the card through the CLK contact. The signal had a frequency in the range from 1 to 5 MHz. In practice, two frequencies are widely used - 3.579545 and 4.9152 MHz. The popularity of these clock frequency values is associated, firstly, with the cheapness of crystals generating such frequencies, and secondly, with the fact that the considered frequency values have integer dividers (372 and 512, respectively), which makes it easy to implement the common in card communications baud rate 9600 bps.
The cheapness of crystals was determined by their widespread use in industry. For example, crystals with a frequency of 3.579545 MHz are used to transmit the color subcarrier in the American television standard NTSC. It is for this reason that most terminals have readers using the mentioned frequencies. Modern readers generate an external clock signal with a frequency of 1 to 10 MHz when establishing a connection with a card.
On the other hand, low external clock rates have become a bottleneck over time for improving performance. Retrofitting a large fleet of terminals to replace higher clock speed readers was difficult and costly. The solution to the problem was the use of the microcircuit's own clock or the use of special hardware and software of the microcircuit to increase the clock frequency of the external generator by an integer number of times. Most often, in modern microcircuits, the processor and other components of the microcircuit operate at the clock frequency of the internal clock of the chip,
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and the input clock signal is used only for communication between the card and the terminal. At the same time, the universal asynchronous transceiver of the microcircuit (UART) supports the frequency multiplication of the external signal in order to ensure the required data transfer rate between the reader and the card.
The architecture of the IPC processor is mainly determined by the system of commands used and addressing methods. Microprocessor cards mainly use RISC processors that support Reduced Instruction Set Computer (RISC). This set usually consists of 20-80 commands, which include arithmetic operations, logical commands, address operations, data transfer commands, I / O commands, control commands, etc. The command system has been simplified and reduced to such an extent that each the command is executed in one clock cycle. This approach improves processor performance.
Today, the Motorola 6805 and Intel 8051 instruction sets are typical of many processors. These instruction sets usually have an addition of memory and register operations, support for addressing and I / O modes, and instructions used exclusively in smart cards.
The largest manufacturers of microprocessors for smart cards are Infineon Technologies AG, Renesas Technology (a joint venture between Hitachi and Mitsubishi), STMicroelectronics, NXP Semiconductors, Motorola, NEC, Atmel, Samsung Electronics.
In microprocessor cards, symmetric and asymmetric cryptographic algorithms are used to ensure the integrity and confidentiality of transmitted data, authenticate the information source, and calculate cryptograms (data signatures consisting of card, terminal and transaction details) (see Appendix B). As a symmetric encryption algorithm, in the overwhelming majority of cases, the block algorithm Triple DES (or 3DES) is used, which has a key length of 112 bits and encrypts blocks of 64 bits. As an asymmetric encryption algorithm, the RSA algorithm is used with a public key modulus ranging from 1024 to 1984 bits.
The symmetric encryption algorithm is based on the use of permutations, substitutions and nonlinear table transformations of individual elements of the encrypted data blocks (see Appendix B). These are simple operations that can be accomplished in a reasonable amount of time using the standard instruction set of the card's CPU. For example, encrypting a 64-bit block with DES (used three times in 3DES) on an 8-bit 3.57 MHz processor takes about 10 ms and requires about 1 KB of ROM to store the DES program and related to it static data (tables of substitutions, permutations and S-transformations). The same encryption operation on a 32-bit 33 MHz processor takes about 100 μs.
To increase the speed of cryptographic computations, microcircuits use special processors called cryptographic coprocessors or cryptoprocessors. Crypto processors are designed to perform a reduced set of special operations used in cryptographic algorithms. In the case of a cryptoprocessor for the implementation of the 3DES algorithm, such operations are the already mentioned permutations, substitutions, and table transformations. Due to the support of a limited set of special operations, the execution time of cryptographic algorithms on a cryptoprocessor is reduced. For example, the implementation of DES on a 33 MHz cryptoprocessor takes 3.5 microseconds, which is about 30 times faster than on a 32-bit CPU with the same clock speed.
Considering that the EMV application during the processing of an online transaction can use the DES algorithm more than 40 times (outputting session keys, ICC Dynamic Number values, calculating ARQC and TC / AAC cryptograms, MAC (Message Authentication Code) verification in Issuer Script Processing commands, encryption of offline counters; for more details, see Chapter 4) even in modern microcircuits using high values of the internal clock frequency, it is customary to use cryptoprocessors - accelerators of the 3DES algorithm. At the same time, it should be recognized that for many applications, including EMV, on modern microcircuits the 3DES algorithm can also be implemented by the microcircuit's central processor.
The situation changes radically in the case of the RSA algorithm. It is known that the implementation of an asymmetric encryption algorithm takes two orders of magnitude (about 100 times) more time than a symmetric one with the same cryptographic strength. The RSA algorithm actively uses block-wise multiplication of two large numbers modulo a large number. This operation requires the presence in the processor instruction system of non-standard instructions for block multiplication and decreasing the obtained
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result by a multiple of some large fixed number. Without support for such special commands, a standard 8-bit processor on the microcircuit will execute the RSA algorithm using a 1024-bit public key module for 10-20 seconds. Taking into account that the total transaction processing time should not exceed 3 s, the option of using the main processor of the microcircuit for RSA implementation immediately disappears.
As a result, a cryptographic coprocessor is used, which allows, when operating at a clock frequency of 33 MHz, to perform encryption on a private (long) key in tens of milliseconds and on an open (short) key in a few milliseconds. Generation of an RSA key pair occurs in less than 10 seconds. The data presented refers to computations with a public key modulus of 1024 bits.
Table 2.1 shows the values of the encryption time on the private and public keys of the RSA algorithm with a public key modulus of 1024 bits for some Infineon microcircuits.
Tab. 2.1. Typical values of the execution times of the RSA algorithm
| SLE66C (X) ... P | SLE66C (X) ... PE | SLE88CX | SLE88CFX | |
| Long key encryption time (ms) | 290 | 130 | 78 | eighteen |
| Short key encryption time (ms) | ten | 5 | 2.8 | 0.5 |
Table 2.2 shows the execution times of various operations of the RSA algorithm on the Crypto @ 1408Bit crypto processor used in the SLE88CFX1M00P and SLE88CFX8002P microcircuits from Infineon. This crypto processor has its own 880 bytes RAM.
Tab. 2.2. Execution Timing RSA
| Operation type | Module size (bits) | Exhibitor size | Execution times (ms) | ||
| 5 MHz | 33 MHz | 66 MHz | |||
| Generating keys | 1024 | 1024 | 5940 | 900 | 450 |
| RSA signature | 1024 | 1024 | 145.2 | 22 | eleven |
| RSA Signature Verification | 1024 | 17 | 16.5 | 2.5 | 1.25 |
| Generating keys | 2048 | 2048 | 46200 | 7000 | 3500 |
| RSA signature | 2048 | 2048 | 594 | 90 | 45 |
| RSA Signature Verification | 2048 | 17 | 132 | twenty | ten |
Note that the speed of RSA operations is linearly dependent on the clock frequency of the crypto processor. The generation time for RSA keys is a random variable (see the description of the algorithm in Appendix B), therefore the table shows the average values of this indicator. Finally, note that the exponent value of the public key F_4 is used = 2 16 + 1 = 65537 (Fermat's number is 2 2 + 1 for n = 4).
Cryptographic coprocessors are designed to perform arithmetic operations on large numbers and have their own RAM for performing such operations. The presence of a cryptographic coprocessor in a chip means an increase in the size of the chip, and hence an increase in the cost of the card. Today, this rise in price is on average 20-30 eurocents per card when purchasing a batch of 10,000 cards (with an increase in the volume of purchases, the difference decreases).
When a smart card implements a number of procedures, random numbers generated by the card are used. An example is the procedures for generating an RSA public / private key pair and encrypting the cardholder PIN. An algorithm or procedure for generating random numbers is usually implemented in a separate module on the chip called a Random Number Generator (RNG). Of course, the concept of an algorithm, each step of which gives a deterministic result, contradicts the concept of randomness. Therefore, RNG software implementations have an inherent flaw and generate only pseudo-random numbers. However, if the range of values of the pseudo-random number generator and the period of their repetition are large, then such an implementation can be considered acceptable.
Along with software implementations of the random number generator, there are hardware implementations that use physical variable parameters of the microcircuit, for example, the characteristics of the thermal noise of the microcircuit. Hardware implementation is preferable to software implementation, since it generates a sequence of numbers that cannot be calculated using any deterministic algorithm. In this sense, the numbers obtained are truly unpredictable, that is, random. Therefore, microcircuit modules that implement random number generators in hardware are called True Random Generator (TRNG). FIPS 140-2 (Federal Information Processing Standards, Publication 140-2) describes randomness tests for a sequence of numbers generated by a random number generator.
To implement a random number generator in a microcircuit, a separate coprocessor is usually used.
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A separate coprocessor is also used to implement the module for calculating the check sequence of a cyclic code described by the ISO / IEC 3309 standard. (For the characteristics of this code and its use in the T = 1 communication protocol, see clause 2.4.2.) This module can also be used for ensuring the integrity of the information stored in the EEPROM memory.
The cheapest type of non-volatile memory is ROM (Read-Only Memory). This memory is also known as ROM (Read Only Memory). In it, an array of cells is a set of conductors organized into a matrix structure (some conductors are rows of such a structure, and some are columns). Some conductors remain intact, and some are destroyed during the "burning" of the ROM mask corresponding to the application that will be stored in the ROM.
The closed state of the conductor can be assigned the value of a logical zero, and the open state - a logical one. If we now measure the voltage between one of the lines of the columns and one of the lines of the rows (i.e., access a specific memory cell), then its high value (open state of the conductor) corresponds to a logical unit, and zero (closed state of the conductor) to logical zero ...
There are other ways to create a ROM mask. The most famous of these is the Implantation ROM method, in which the memory is encoded by irradiating the surface of the crystal occupied by the ROM with a powerful ion beam.
The main disadvantage of ROM is the impossibility of updating the contents of memory cells, i.e., the impossibility of recording / updating information during the operation of the card. Therefore, in smart cards, ROM is loaded with the operating system of the card and static applications (applications that do not require changes during the life cycle of the card). In particular, ROM stores all utility programs, including programs for maintaining the file system of the card and providing communication, performing cryptographic operations. These programs are written ("stitched") into the ROM during the manufacture of the card and cannot be changed later.
General purpose smart cards have ROMs ranging in size from 16 to 196 KB. The ROM size in record-breaking cards exceeds 256 Kb.
RAM (or otherwise operating memory) is the volatile and most expensive memory in a smart card.
It is used by the processor to store fragments of executable code and intermediate data when performing various operations, since it is the fastest form of memory for reading and writing data. The access time (the period of time during which the contents of one memory cell can be read or written) of RAM is several tens of nanoseconds. The speed of processor operations depends on the size of the RAM memory (sometimes, due to the small size of the RAM memory, you have to split one operation into several sequential operations, which increases the execution time).
Hard limits on RAM size are the most sensitive in terms of writing card applications. Even the use of high-level languages makes developing smart card applications an art to be learned. The programmer is constantly forced to economically use temporary variables or even invent special algorithms to implement operations using large variables.
Moreover, RAM is used by both the programmer's applications and all the utilities of the card, and the programmer must know not only how much RAM is used by his applications, but also how much memory is required for the utilities that his applications access during their execution. This is why, despite the emergence of open platforms Java Card and MULTOS, enabling millions of software developers to write smart card applications, this is still the domain of smart card vendors.
As shown in fig. 2.5, the size of the crystal areas occupied by RAM and ROM, necessary to store the same amount of information, are approximately 16: 1. To a first approximation, the cost of a microcircuit component is proportional to the area of the crystal it occupies. Therefore, the increase in the cost of the card with the increase in the size of the RAM memory is the fastest in comparison with other types of memory.
Champion cards (usually Java cards) have a RAM size of 4 to 8 KB, although for many payment applications (supporting only DES and T = 0 protocol) it is sufficient to have a memory size of several hundred bytes. Record-breaking cards (for example, the already mentioned cards of the SLE88 family from Infineon) have 16 KB of RAM, and the SLE88CNFX6602PM card even has 32 KB.
There is another type of non-volatile rewritable memory widely used in smart cards - EEPROM memory. Unit
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this memory is about four times cheaper than a RAM unit and four times more expensive than a ROM unit. The EEPROM can house some of the card applications, as well as store the operating system data of the card and all configuration and variable data of the card applications, regardless of whether these applications are stored in ROM or EEPROM. Obviously, this is due to the fact that EEPROM is the only rewritable and at the same time non-volatile type of memory on a smart card. When the card is powered off, the data written to the EEPROM can be stored for more than ten years.
EEPROM memory has two significant limitations. The first is the limited memory performance. It usually takes 2 to 10 ms to erase and then write data to the EEPROM (programming time).
The second limitation is related to the wear and tear of this type of memory. EEPROM memory becomes unusable after a certain number of data rewriting cycles (about 100-500 thousand cycles).
Recently, card manufacturers have been paying more and more attention to flash memory as an alternative to ROM and EEPROM. This type of memory is about twice as economical as EEPROM memory and twice as expensive as ROM memory. At the same time, flash memory has many important advantages. As compared to EEPROM memory, the advantages of flash memory lie in a significant increase in the speed of memory and in the absence of its wear (you can rewrite data almost an unlimited number of times).
Compared to ROM, the main advantage of flash memory is that it eliminates the need to create a map mask. The operating system of the card and applications can be loaded into flash memory just like normal software. In this case, the area of the flash memory used as a ROM, after downloading the software, for security reasons must be securely closed against changes / modifications.
An important issue for the use of smart cards is the problem of ensuring the integrity of the information stored on the card when the transaction is interrupted. Since the card can be removed from the terminal's reader at any time during the execution of a transaction, this can happen in the middle of the calculations associated with the card's implementation of some function of its application. This card extraction is called a break. If a rupture has occurred, it is important that the information in the microcircuit does not remain in a state of unfinished operation. In particular, if the card supports the functionality of an electronic wallet, then it is important that upon a rupture, the amount of the wallet does not turn out to be higher than at the beginning of the operation. Otherwise, it will become an obvious way of committing fraud.
A number of gap-bridging mechanisms are employed in smart cards. The most general is a mechanism similar to the mechanism adopted in database management systems and consists of the following. At the beginning of the operation, the "transaction flag" is set and the most important application parameters at that moment are stored in the EEPROM. This flag and its associated data are cleared only at the end of the operation. If at the beginning of the next operation a set "transaction flag" is noticed, this will indicate that the previous transaction was aborted and not completed. When this state is recognized, the application settings are "rolled back" to the state at the beginning of the previous transaction, and only then the new operation starts.
The integrity of the most important information stored on the card, such as keys, cardholder personal data, etc., is ensured by the card's hardware and software. Special sensors of the microcircuit prohibit changing the memory of the microcircuit if the processor does not process the data write command. In addition, the operating system of the card uses check sequences to detect the fact that the integrity of the stored information has been violated.
The I / O channel of the smart card chip is a unidirectional serial interface. This means that at a time, only 1 bit of information can be transmitted along it and it can only be transmitted in one direction (half-duplex communication). In accordance with the ISO / IEC 7816-3 standard, data exchange between the smart card and the reader can be carried out at a speed of up to 115,200 bps. Modern contact cards support baud rates of 9600, 19,200, 38,400, 55,800, 76,800 bps and higher. The baud rate supported by the card is determined by the ability of the asynchronous transceiver to multiply the frequency of the external clock signal or internal clock (see section 2.3). Many UARTs support 4x, 8x, 16x clock frequency multiplication.
To organize data transfer between the reader and the card, two lines of the card interface are used. One of the lines, the I / O line (I / O lines), carries the data bits. The second line, the clock line (CLK line), indicates when to sample the I / O line to obtain a data bit.
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The USB interface uses two additional lines to form a second I / O channel. In this way, a duplex connection is created.
A duplex SWP (Single Wire Protocol) connection is established over one line using pin C6. The typical data exchange rate for such a connection is 1.5 Mbit / s.
The communication protocol between the reader and the smart card uses the relationship between the user (reader) and the server (smart card). The reader sends commands to the card and receives responses from it. The smart card never sends data to the reader, except in response to his command.
The standard link layer protocols (T = O, T = 1, T = CL) used between the reader and the card are half duplex. This means that data is either supplied to the I / O line by the reader and read by the card, or supplied by the card and read by the reader. Thus, each participant in the data exchange (reader and terminal) keeps track of whether it is in the transmitting state or in the receiving state.
The communication protocols used are not complex, and therefore complete - taking into account all possible situations. Therefore, a case is possible when, for example, the reception of an erroneous message leads one or both sides of the data exchange to an undefined state. When this happens, it is the responsibility of the reader to restart the card to correct the line failure.
Smart card operating systems support character-by-character and / or block-by-block communication. (For more details, see section 2.4.)
There are smart cards on the market that support work with the terminal via the USB protocol, which provides full-duplex data transfer at speeds up to 12 Mbit / s. It should be noted that the weak communication capabilities of today's microprocessor cards are one of the main limitations for expanding the area of their use. Improving the communication characteristics of a smart card (duplex nature of the exchange, support for a stack of Internet protocols, including TCP / IP, increasing the data transfer rate) will make a smart card an independent device capable of direct dialogue with network computers.
Power is supplied to the card from the reader. All smart cards used today can operate at a supply voltage of 5 volts and 3 volts (more precisely, in accordance with section 5.3.6 of book 1 of the EMV 4.2 standard, the card must support voltages in the range from 4.5 to 5.5 volts and from 2, 7 to 3.3 volts). Some microcircuits are capable of operating at lower supply voltages, namely at 1.8 volts.
In June 2009, the migration of cards supporting only 5 volt supply voltage to cards supporting two voltage values - 5 and 3 volts, and cards supporting three voltage values - 5, 3 and 1.8 volts was completed. Thus, cards supporting a single supply voltage of 5 volts are out of circulation.
As a result, today servicing banks / merchants can install terminals that support only 3 volts or two voltage values - 3 volts and 1.8 volts. However, terminals that only support 5 volts remain functional and there are no plans to retire these terminals. To date, EMVCo, the company that manages EMV specifications, has not developed a plan to start installing terminals whose readers only support 1.8 volts.
The choice of the operating voltage value supplied to the card is determined as follows. If the terminal supports multiple supply voltages, the smallest value (1.8 or 3 volts) is applied to the VCC pin of the microprocessor card. If a voltage of 1.8 volts was applied and within a certain time interval the terminal does not receive an ATR sequence from the card (see p. 2.3), it supplies the card with a supply voltage of 3 volts.
